The present invention relates to a dynamic memory circuit, and more particularly to a dynamic type semiconductor memory circuit employing flip-flop type sense amplifiers.
Dynamic memories are widely utilized in various fields as large capacity memories. A dynamic memory generally comprises a large number of memory cells in a matrix form of rows and columns, word lines in rows and digit lines in columns. In reading or refreshing operation, memory cells coupled to the selected word line cause small potential changes in the digit lines. Such small potential changes in the digit lines or digit line pairs are amplified by sense amplifiers ad the amplified signals are rewritten into the memory cells coupled to the selected word line. In writing operation, a write data signal is applied via the selected digit .line or digit line pair to the selected memory cell while the sense amplifier coupled to the selected digit line or digit line pair is enabled. The sense amplifier is generally comprised of a flip-flop type differential amplifier and the digit line of a lower potential in the digit line pair is discharged through the sense amplifier to a sense amplifier activation signal line in response to the change from a high level corresponding to a precharge level of the digit line to a low level in that line. Thus, the digit line of the lower potential becomes at the minimum level such as the ground potential thereby to achieve amplification or refresh of the read out signal of the selected memory cell.
Recently, there has been proposed a memory in which columns are classified into a plurality of column blocks with the common rows and each column block is provided with a read-write circuit. In such memory, writing of data into one column block and refreshing of contents of memory cells of other column blocks are simultaneously performed. In the above operation, a relatively large signal is applied to the column block performing a write operation and therefore the state of the sense amplifier or amplifiers in the above column block are determined rapidly. While, small signals are produced on digit lines from the memory cells in other column blocks performing refresh operation. Therefore, sense amplifiers in the above other column blocks are required to discharge the lower potential of digit lines gradually to the sense amplifier activation signal line.
However, the rapidly established states of the sense amplifiers in the column block performing write operation adversely affect the sense amplifier activation signal line to change the potential at that line to the low level in an unexpectedly short period of time Therefore, the sense amplifiers in the above other column blocks fail to accurately amplifying small read-out signals on the digit line, resulting in insufficient or erroneous refresh operation.